Please use this identifier to cite or link to this item: http://hdl.handle.net/10419/201745
Authors: 
Mohamed, Belal
Shalaby, Ahmed
Sayed, Mohammed S.
Year of Publication: 
2019
Series/Report no.: 
2nd Europe - Middle East - North African Regional Conference of the International Telecommunications Society (ITS): "Leveraging Technologies For Growth", Aswan, Egypt, 18th-21st February, 2019
Abstract: 
Motion estimation entails the major computation complexity load and processing time in HEVC video encoder. Integer-pixel Motion Estimation (IME) consume more than 45% of the processing time. Therefore, this paper presents a High-Level Synthesis Hardware Accelerator for Integerpixel Motion Estimation of HEVC on Xilinx SoC-FPGA Platform. The hardware accelerator is three time faster than the corresponding software implementation with only 100 MHz clock frequency on Xilinx Zynq ZC702 FPGA.
Document Type: 
Conference Paper

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